As is known, and as illustrated schematically in FIG. 1, a non-volatile memory device, designated by 1, here of a phase change type, in general comprises a memory array 2 including a plurality of memory cells 3 arranged in rows and columns and storing respective data.
Each memory cell 3 is here formed by a storage element 4 of a phase change type, designed to store a binary datum, and by a selection element 5, here formed by an NMOS transistor, in series to the storage element 4. The selection elements 5 for memory cells 3 arranged in a same row have gate terminals coupled together and to a respective word line WL0, WL1, . . . . The selection elements 5 of memory cells 3 arranged in a same column have respective first conduction terminals coupled together and to a respective local bit line LBL1, . . . , LBLn, . . . . Each selection element 5 moreover has a second conduction terminal, coupled to a reference-potential line (for example, connected to ground).
The local bit lines LBL0, . . . , LBLi, . . . are coupled to a column decoding stage 6, illustrated in a simplified way, in turn coupled to a biasing and reading circuit 7, only a sense amplifier stage 12 thereof is illustrated. The word lines WL0, WL1, . . . are coupled to a row-decoding stage 8 illustrated schematically in FIG. 1. In a known way, the biasing and reading circuit 7, the column decoding stage 6, and the row-decoding stage 8 allow selection of one or more memory cells 3 each time on the basis of address signals generated by a control unit 10 (also represented schematically).
In the example illustrated, the memory 1 has a hierarchical bit line structure (in the simplified example, with two levels, but three levels could be envisaged), where the local bit lines LBL1, . . . , LBLi, . . . are coupled, through first switches 13.0, 13.1, . . . , to global bit lines (also referred to as “main bit lines”) MBL0, MBL1, . . . , which are, in turn, coupled to the biasing and reading circuit 7 through second switches 14.0, 14.1, . . . . In the schematic representation of FIG. 1, the first switches 13.0, 13.1, . . . , the second switches 14.0, 14.1, . . . , and the global bit lines MBL0, MBL1, . . . form the column decoding stage 6. In some embodiments, as referred to above, the column decoding stage 6 may comprise a further hierarchical level, with further bit lines and corresponding third switches, in a way known to the person skilled in the art and not illustrated.
The biasing and reading circuit 6 forms in particular one or more reading paths, which may be activated individually or in parallel, and each whereof is designed to create a conductive path between the memory cells 3 of the memory array 2 each time selected and the sense amplifier stage 12. The latter is of a differential type and is intended to compare the current circulating in the selected memory cell 3 with a reference current in order to determine the value of the datum stored and generate a corresponding digital reading signal.
Recently, the use of memory devices produced in the back-end steps of the process, the storage element whereof is provided in the last layers of the device, has assumed greater importance due to the possibility of simplifying the manufacturing process and consequently reducing the manufacturing costs, affording memory devices of an embedded type, possibly integrated in a same die with other circuits and obtained in an advanced CMOS technology.
In particular, back-end integration of non-volatile phase change memory devices becomes increasingly important. In these memory devices, the storage element is formed by a region of a material that, when subjected to adequate current values, is able to change its own physical structure, passing from an amorphous phase to a crystalline phase and vice versa, with consequent variation of its ohmic resistance. This variation of ohmic resistance is used for storing digital data.
The two states of the storage element are known as:
the SET state, associated to the crystalline phase characterized by a lower resistance, and thus, in case of constant-voltage reading of the storage element, by a higher current; and
the RESET state, associated to the amorphous phase characterized by a higher resistance, and thus, in case of constant-voltage reading of the storage element, by a lower current.
In this type of memory, phase transition in the storage element is activated in temperature and is obtained by applying a current pulse having a duration of a few microseconds, which, by the Joule effect, locally raises the temperature and modifies the physical structure of the material.
This type of memory device is thus potentially sensitive to problems of data retention, which emerge in particular when the device is exposed to intermediate temperatures, even not very high ones (up to 165° C.), but for long times (up to a few thousand hours). This frequently occurs, for example, when the memory device is used for automotive applications and thus normally functions at temperatures of 150-160° C.
In particular, in this situation, the phenomena that may arise and may lead to failure or in any case to incorrect operation, are linked to the loss of the amorphous and crystalline states (associated to the conditions of reset and set), due to partial crystallization, i.e., to passage to a less orderly crystalline condition of the material that is in the amorphous or crystalline phase.
For applications where the temperature plays a fundamental role, the type of material chosen, and in particular its composition, may be optimised so as to meet requirements of reliability and retention of the data.
However, also in this case, application of intermediate temperatures may lead to a non-negligible phase variation of the optimised material, leading to a progressive reduction of the difference between the values of current, or resistance, associated to the two states of the memory.
The phenomenon may be highlighted considering the normalised distribution of the number N of cells as a function of the reading current Ir and following evolution thereof in time at constant temperature, as illustrated in FIG. 2A in case of memory cells programmed in the reset state and in FIG. 2B in case of memory cells programmed in the set state and kept at a constant temperature of 150° C. from the programming instant in the reset and set state (ts=0).
In particular, in these figures, the curves A1 and A2 represent the cumulative distributions of the reset and set cells, respectively, that conduct reading currents up to the values Ir reported at time zero, and the other curves represent similar cumulative distributions of memory cells conducting reading currents up to the values Ir, plotted after progressively increasing times from programming (as indicated by the arrows), from 3 h (curves B1 and B2, respectively) up to 2000 h (curves C1 and C2, respectively).
As may be noted, both the distribution of the reset cells and the distribution of the set cells shift, with increasing time elapsed since programming thereof, towards the left, i.e., towards lower current values. This phenomenon is particularly important in case of the set cells (FIG. 2B), which shift from values of the reading current comprised between 22 μA and 30 μA, to much lower current values, as little as 5 μA, after 2000 h.
The worst cells of the distributions, defined as the ones that cannot be recovered by the error-correction reading scheme, can be identified at the intersection between the distributions and the equiprobability straight line ECC (set at 10−6 in the example of FIGS. 2A and 2B).
This means that, without reprogram or refresh, the difference of reading current between the worst cells that have been set long before reading thereof (and have, for example, reading currents of a few milliamps) and the worst cells that have been reset recently is very low or even zero.
This fact is highlighted by the curves D1 and D2 of FIG. 3, which present the data of FIGS. 2A and 2B as a function of the storage time ts (at a fixed temperature) for the worst cells in the distributions of reset and set cells, kept at 150° C. after programming thereof at ts=0, up to a time of approximately 1000 h. The distance between the two curves D1 and D2 thus represents the reading window for the memory.
In particular, FIG. 3 shows that, for ts=0, the difference between the reading currents of the worst set cells and of the worst reset cells is high and that this difference tends to decrease in time due to the temperature applied.
FIG. 4 presents at an enlarged scale a portion of FIG. 3, where the arrows indicate the differences of reading currents Ir at different storage times ts, and shows a grey area representing a “free” range of reading currents Ir, i.e., one without set or reset cells.
The above range represents a working window of approximately 1 μA, which is clearly set apart from the curves D1 and D2 for low values of storage time ts, but then approaches the curve D2 of the worst set cells and reaches it for a storage time a little higher than 1000 h. After this time, in case of fast reading, i.e., of a few nanoseconds, the working window overlaps the curve D2 of the worst set cells and thus does not enable reading with a sufficiently low error margin. With this working window it is thus necessary to re-program the cells via a refresh operation after a maximum time of 1000 h.
Also in this way, reading of the cells would be problematical. In fact, in memories of a NOR flash type, reading is in general carried out by comparing the reading current Ir with a reference current, generated by a reference cell formed in the same memory array so as to have the same electrical characteristics or generated by an equivalent current source.
In theory, the reference current could be variable in time, as a function of the programming time, or constant.
However, in case of a reference current that is variable in time, it would be necessary to trace the time that has elapsed since programming of the cell to be read and adapt the characteristics of the reference element to be in the middle of the working window of FIG. 4. This solution is not, however, practicable, since tracing the programming time of each cell would be complex and entail high costs and unacceptable reading times.
On the other hand, reading via a fixed reference proves complex at high reading speeds (current requirements call, for example, for a reading time of approximately 10 ns). In fact, for instance, a same memory array could comprise a cell that has been set for almost 1000 h and has a reading current a little higher than 6 μA and a cell that has just been reset, with a reading current a little lower than 5 μA. The reference current could thus be set half-way between these values, for example at 5.5 μA. In this case, the reading circuit could be designed so as to be able to distinguish a reading current of 5 μA with respect to a reference at 5.5 μA or a reading current of 6 μA with respect to the same reference at 5.5 μA.
In practice, this entails being able to distinguish currents that differ by 0.5 μA, which is already difficult in itself at the considered reading rates. In addition, the above resolution is a fraction of the read currents, both for the set cells and for the reset cells, whereby the problem is more complex and some fast reading solutions used for other types of memory are inapplicable.
For instance, in Italian patent application 102016000024496 filed in the name of the present applicant (corresponding to the U.S. Pat. No. 9,865,356 and to European patent application EP 3 217 405) a reading method and circuit are described wherein the voltage across the selected bit line is compared with the voltage across an adjacent bit line pre-charged at an intermediate value between the values that can be reached by the selected bit line in the two states stored by the memory cell to be read. In particular, the reading method disclosed in this patent application, described with reference to floating-gate flash cells, exploits the parasitic capacitances existing in the memory array and consists in charging two global bit lines (that of the cell to be read and that of an adjacent bit line) at the intermediate value. Then, the cell to be read is read. If this cell stores a bit “1”, it conducts current and causes discharging of its own local bit line and thus, by charge sharing, of its own global bit line, bringing the latter to a lower voltage value than the intermediate value on the adjacent global bit line. If the cell to be read stores a bit “0” and thus does not conduct current, its local bit line does not discharge, but brings its own global bit line to a higher voltage value than the intermediate value on the adjacent global bit line.
The reading circuit described in the above Italian patent application 102016000024496 operates very well when one of the two programming states is characterized by a zero current, as occurs, for example, for the mentioned application of floating-gate flash cells, but is not usable when a common current contribution is present, as in case of a memory cells of a PCM type having the electrical behaviour discussed above.
The aim of the present invention is to provide a reading circuit and method that overcome the limitations of the prior art.